PortMatcher.h

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//===- PortMatcher.h - Matching Ports -------------------------*- C++ -*-=====//
//
// Part of the systemc-clang project.
// See License.rst
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
 
#ifndef _PORT_MATCHER_H_
#define _PORT_MATCHER_H_
 
#include <vector>
#include "ModuleInstance.h"
#include "PortDecl.h"
#include "ArrayTypeUtils.h"
 
#include "clang/ASTMatchers/ASTMatchers.h"
 
#undef DEBUG_TYPE
#define DEBUG_TYPE "PortMatcher"
 
using namespace clang::ast_matchers;
 
namespace sc_ast_matchers {
 
using namespace utils::array_type;
 
//
//
 
class PortMatcher : public MatchFinder::MatchCallback {
 public:
  typedef std::vector<std::tuple<std::string, PortDecl *> > MemberDeclType;
 
 private:
  //std::string top_module_decl_;
 
 public:
  MemberDeclType clock_ports_;
  MemberDeclType in_ports_;
  MemberDeclType out_ports_;
  MemberDeclType inout_ports_;
  MemberDeclType other_fields_;
  MemberDeclType signal_fields_;
  MemberDeclType instream_ports_;
  MemberDeclType outstream_ports_;
  MemberDeclType sc_ports_;
 
  MemberDeclType submodules_;
 
 public:
  
  const MemberDeclType &getClockPorts() const { return clock_ports_; }
  
  const MemberDeclType &getInputPorts() const { return in_ports_; }
  
  const MemberDeclType &getOutputPorts() const { return out_ports_; }
  
  const MemberDeclType &getInOutPorts() const { return inout_ports_; }
  
  const MemberDeclType &getOtherVars() const { return other_fields_; }
 
  const MemberDeclType &getSignals() const { return signal_fields_; }
 
  const MemberDeclType &getSubmodules() const { return submodules_; }
  
  const MemberDeclType &getInputStreamPorts() const { return instream_ports_; }
 
  const MemberDeclType &getOutputStreamPorts() const {
    return outstream_ports_;
  }
 
  const MemberDeclType &getPorts() const { return sc_ports_; }
 
  PortMatcher() {}
 
  auto makeFieldMatcher(llvm::StringRef name) {
    /* clang-format off */
 
  return  cxxRecordDecl(
    isExpansionInMainFile(),
    isDerivedFrom(hasName("::sc_core::sc_module")),
    forEach(
      fieldDecl(hasType(
            cxxRecordDecl(hasName(name))
          ) // hasType
        ).bind(name) // fieldDecl
      )
    );
  }
 
  auto makeSignalArrayType(const std::string &name) {
    return arrayType(
     hasElementType(
       hasDeclaration(
        cxxRecordDecl(isDerivedFrom(hasName(name))).bind("desugar_"+name)
        )
      )
    ).bind("array_type");
  }
 
  auto signalMatcher(const std::string &name) {
  return anyOf(
    hasType(makeSignalArrayType(name))
    ,
    // 2-d
    hasType(
      arrayType(
        //hasElementType(
        hasElementType(hasUnqualifiedDesugaredType(
          makeSignalArrayType(name) 
          )//hasElementType
          )
        )//arrayType
      )//hasType 
    ,
    // 3-d
    hasType(
      arrayType(
        //hasElementType(
        hasElementType(hasUnqualifiedDesugaredType(
          arrayType(
            hasElementType(
              makeSignalArrayType(name)) 
            ) //arrayType
          )
          ) //hasElementType
        )//arrayType
      )//hasType
    ,
    // Regular field declaration
    hasType(
      cxxRecordDecl(isDerivedFrom(hasName(name))).bind("desugar_"+name)
      )
    ,
    hasType(pointerType(pointee(hasDeclaration(cxxRecordDecl(isDerivedFrom(hasName(name))).bind("desugar_"+name)))))
    );
  }
 
  auto makeSignalMatcher(llvm::StringRef name) {
    return fieldDecl(
        signalMatcher(name.str())
      ).bind("other_fields");
  }
 
  auto makeArrayTypeMatcher(const std::string &name) {
    return   recordType(hasDeclaration(cxxRecordDecl(hasName(name)).bind("desugar_"+name)));
   
  }
  auto portNameMatcher(const std::string &name) {
      return 
          anyOf(
            hasType(
              arrayType(
 
                anyOf(
 
                  // 1-d
                hasElementType(hasUnqualifiedDesugaredType(
                    recordType(
                      hasDeclaration(
                        cxxRecordDecl(hasName(name)).bind("desugar_"+name)
                      )
                    )
                  )
                )//hasElementType
 
                ,
 
                // 2-d
                hasElementType(hasUnqualifiedDesugaredType(
                    arrayType(hasElementType(hasUnqualifiedDesugaredType(
                          makeArrayTypeMatcher(name)
                          ))
                      )//arrayType
                  )
                )//hasElementType
 
                  ,
                //3-d
 
                hasElementType(hasUnqualifiedDesugaredType(
                    arrayType(hasElementType(hasUnqualifiedDesugaredType(
                          arrayType(hasElementType(hasUnqualifiedDesugaredType(
                            makeArrayTypeMatcher(name)
                          ))
                            )//arrayType
                          ))
                      )//arrayType
                  )
                )//hasElementType
 
 
                )//anyOf
              )
            ),
            hasType(hasUnqualifiedDesugaredType(
                  anyOf(
                recordType(
                  hasDeclaration(
                    cxxRecordDecl(hasName(name)).bind("desugar_"+name)
                  )
                )
                ,
                pointerType(pointee(
                  hasDeclaration(
                    cxxRecordDecl(hasName(name)).bind("desugar_"+name)
                  )
                    ) // pointee
                  )
                )
 
              )
            )
          );
  }
 
  auto makePortHasNameMatcher(llvm::StringRef name) {
    return fieldDecl(
        portNameMatcher(name.str())
        ).bind("other_fields");
  }
 
  auto makePortHasNamedDeclNameMatcher(llvm::StringRef name) {
    return 
      fieldDecl(
          anyOf(
            hasType(arrayType(hasElementType(asString(name.str())))),
            hasType(namedDecl(hasName(name.str())))
          )
      );
  }
 
  auto makeArraySubModule(llvm::StringRef name) {
    return arrayType(
     hasElementType(hasUnqualifiedDesugaredType(
         recordType(
           hasDeclaration(
            cxxRecordDecl(isDerivedFrom(hasName(name.str()))).bind("submodule")
            ) //hasDeclaration
         )// recordType
       ))
     );
  }
 
  auto makeMemberIsSubModule() {
    llvm::StringRef base_class{"::sc_core::sc_module"};
 
    return
      fieldDecl(
          hasType(hasUnqualifiedDesugaredType(
              anyOf(
                // 1 instance
                recordType(
                  hasDeclaration(
                    cxxRecordDecl(
                      isDerivedFrom(hasName("::sc_core::sc_module")),
                      unless(isDerivedFrom(matchesName("sc_event_queue")))
                      ).bind("submodule")
                    ) //hasDeclaration
                  ) //recordType
 
                // 1D array
                ,
                makeArraySubModule(base_class)
 
                // 2D array of modules
                ,
                arrayType(
                  hasElementType(hasUnqualifiedDesugaredType(
                    makeArraySubModule(base_class) 
                    )//hasElementType
                    )
                  )//arrayType
 
                  // 3D array
                ,
                arrayType(
                  hasElementType(hasUnqualifiedDesugaredType(
                      arrayType(hasElementType(
                        makeArraySubModule(base_class) 
                        )//hasElementType 
                      ) // arrayType
                      ) //hasUnqualifiedDesugaredType
                    ) // hasElementType
                  )//arrayType
 
                ) // anyOf
 
              ) //hasUnqualifiedDesugaredType
            ) //hasType
          ).bind("submodule_fd"); // fieldDecl;
 
  }
  /* clang-format on */
 
  template <typename NodeType>
  auto checkMatch(const std::string &name,
                  const MatchFinder::MatchResult &result) {
    return result.Nodes.getNodeAs<NodeType>(name);
  }
 
  void printTemplateArguments(MemberDeclType &found_ports) {
    // Input ports
    for (const auto &i : found_ports) {
      LLVM_DEBUG(llvm::dbgs() << "name: " << get<0>(i) << ", FieldDecl*: "
                              << get<1>(i)->getAsFieldDecl());
      LLVM_DEBUG(
          get<1>(i)->getTemplateType()->printTemplateArguments(llvm::dbgs()));
      LLVM_DEBUG(llvm::dbgs() << "\n");
    }
  }
 
  template <typename T>
  auto parseTemplateType(const T *fd) {
    clang::QualType qual_type{fd->getType()};
    const clang::Type *type_ptr{qual_type.getTypePtr()};
    auto template_ptr{new FindTemplateTypes()};
    template_ptr->Enumerate(type_ptr);
    LLVM_DEBUG(template_ptr->printTemplateArguments(llvm::dbgs()));
    return template_ptr;
  }
 
  template <typename T>
  void insert_port(MemberDeclType &port, T *decl, bool isFieldDecl = true) {
    // port is a map entry [CXXRecordDecl* => vector<PortDecl*>]
 
    std::string name{};
    if (auto *fd = dyn_cast<clang::FieldDecl>(decl)) {
      name = fd->getIdentifier()->getNameStart();
 
      PortDecl *new_pd{new PortDecl(name, decl, parseTemplateType(fd))};
 
      std::vector<llvm::APInt> sizes{ getConstantArraySizes(fd) };
 
      if (sizes.size() > 0 ) {
        new_pd->setArrayType();
        for (auto const &array_size : sizes ) {
          new_pd->addArraySize(array_size);
        }
      }
 
      auto port_entry{std::make_tuple(name, new_pd)};
      port.push_back(port_entry);
 
    } else {
 
      if (auto *vd = dyn_cast<clang::VarDecl>(decl)) {
        name = vd->getIdentifier()->getNameStart();
        PortDecl *new_pd{new PortDecl(name, decl, parseTemplateType(vd))};
 
        auto field_type{vd->getType()};
        auto array_type{dyn_cast<ConstantArrayType>(field_type)};
        if (array_type) {
          new_pd->setArrayType();
          while (array_type != nullptr) {
            llvm::APInt array_size{};
            array_size = array_type->getSize();
            LLVM_DEBUG(llvm::dbgs()
                           << "Size of array: " << array_size << "\n";);
            array_type =
                dyn_cast<ConstantArrayType>(array_type->getElementType());
 
            new_pd->addArraySize(array_size);
          }
        }
 
        auto port_entry{std::make_tuple(name, new_pd)};
        port.push_back(port_entry);
      }
    }
  }
 
  void registerMatchers(MatchFinder &finder) {
    /* clang-format off */
 
    //
    auto match_module_decls = 
      cxxRecordDecl(
          //matchesName(top_module_decl_), // Specifies the top-level module name.
          hasDefinition(),               // There must be a definition.
          unless( isImplicit() ),        // Templates generate implicit structs - so ignore.
          isDerivedFrom(
            hasName("::sc_core::sc_module") 
            ),
          unless(isDerivedFrom(matchesName("sc_event_queue")))
      );      
 
 
    auto match_sc_ports = cxxRecordDecl(
        match_module_decls,
        forEach(
          fieldDecl(
            hasType(
              cxxRecordDecl(isDerivedFrom(hasName("sc_port")))
            )
          ).bind("sc_port")
        )
      );
 
     auto match_all_ports = cxxRecordDecl(
         match_module_decls,
         eachOf(
           forEach(
             makePortHasNamedDeclNameMatcher("sc_in_clk")),
           forEach(
               makePortHasNameMatcher("sc_in")),
           forEach( 
               makePortHasNameMatcher("sc_out")),
           forEach(
               makePortHasNameMatcher("sc_inout")),
           forEach(
             makeSignalMatcher("sc_signal_inout_if")),
           forEach(
               makePortHasNameMatcher("sc_stream_in")),
           forEach(
               makePortHasNameMatcher("sc_rvd_in")),
           forEach(
               makePortHasNameMatcher("sc_rvd_out")),
           forEach(
               makePortHasNameMatcher("sc_stream_out"))
           )
               );
     // Notice that the ports can also be arrays.
     
     auto match_non_sc_types_fdecl = 
      cxxRecordDecl(
      match_module_decls,
      //unless(match_all_ports),
          forEach(fieldDecl(
              unless(portNameMatcher("sc_in_clk")),
              unless(portNameMatcher("sc_in")),
              unless(portNameMatcher("sc_out")),
              unless(portNameMatcher("sc_inout")),
              unless(portNameMatcher("sc_stream_in")),
              unless(portNameMatcher("sc_stream_out")),
              unless(portNameMatcher("sc_rvd_in")),
              unless(portNameMatcher("sc_rvd_out")),
              unless(signalMatcher("sc_signal_inout_if")),
              unless(portNameMatcher("sc_rvd_in")),
              unless(portNameMatcher("sc_rvd_out")),
              unless(makeMemberIsSubModule())
              ).bind("other_fvdecl")));
 
    auto match_non_sc_types_vdecl = cxxRecordDecl(
        forEach(
          varDecl(
          unless(portNameMatcher("sc_in_clk")),
              unless(portNameMatcher("sc_in")),
              unless(portNameMatcher("sc_out")),
              unless(portNameMatcher("sc_inout")),
              unless(portNameMatcher("sc_stream_in")),
              unless(portNameMatcher("sc_stream_out")),
              unless(portNameMatcher("sc_rvd_in")),
              unless(portNameMatcher("sc_rvd_out")),
              unless(signalMatcher("sc_signal_inout_if")),
              unless(portNameMatcher("sc_rvd_in")),
              unless(portNameMatcher("sc_rvd_out")),
              unless(makeMemberIsSubModule())
     
            ).bind("other_fvdecl")));
 
    auto match_submodules = cxxRecordDecl(
        forEach(
          makeMemberIsSubModule()
          )
        );
    /* clang-format on */
 
    // Add matchers to finder.
    finder.addMatcher(traverse(TK_IgnoreUnlessSpelledInSource, match_all_ports) , this);
    finder.addMatcher(traverse(TK_IgnoreUnlessSpelledInSource, match_non_sc_types_fdecl), this);
    finder.addMatcher(traverse(TK_IgnoreUnlessSpelledInSource, match_non_sc_types_vdecl), this);
    //finder.addMatcher(match_submodules, this);
    // finder.addMatcher(match_sc_ports, this);
  }
 
  virtual void run(const MatchFinder::MatchResult &result) {
    auto sc_in_field{checkMatch<clang::CXXRecordDecl>("desugar_sc_in", result)};
    auto sc_out_field{
        checkMatch<clang::CXXRecordDecl>("desugar_sc_out", result)};
    auto sc_inout_field{
        checkMatch<clang::CXXRecordDecl>("desugar_sc_inout", result)};
    auto sc_signal_field{
        checkMatch<clang::CXXRecordDecl>("desugar_sc_signal_inout_if", result)};
    auto sc_stream_in_field{
        checkMatch<clang::CXXRecordDecl>("desugar_sc_stream_in", result)};
    auto sc_stream_out_field{
        checkMatch<clang::CXXRecordDecl>("desugar_sc_stream_out", result)};
    auto sc_rvd_in_field{
        checkMatch<clang::CXXRecordDecl>("desugar_sc_rvd_in", result)};
    auto sc_rvd_out_field{
        checkMatch<clang::CXXRecordDecl>("desugar_sc_rvd_out", result)};
    auto sc_port_field{
        checkMatch<clang::CXXRecordDecl>("desugar_sc_port", result)};
    auto other_fields{checkMatch<clang::Decl>("other_fields", result)};
    auto other_fvdecl{checkMatch<clang::Decl>("other_fvdecl", result)};
 
    // auto array_type{checkMatch<clang::ArrayType>("array_type", result)};
 
    auto submodule_fd{checkMatch<clang::FieldDecl>("submodule_fd", result)};
 
    if (submodule_fd) {
      auto name{submodule_fd->getNameAsString()};
      LLVM_DEBUG(llvm::dbgs() << "Found submodule: " << name << "\n");
      insert_port(submodules_, submodule_fd);
    }
 
    if (sc_in_field && other_fields) {
      if (auto *p_field{dyn_cast<clang::FieldDecl>(other_fields)}) {
        auto fd = p_field;
        auto port_name{fd->getIdentifier()->getNameStart()};
        LLVM_DEBUG(llvm::dbgs() << " Found sc_in: " << port_name << "\n");
        insert_port(in_ports_, fd);
      }
    }
 
    if (sc_out_field && other_fields) {
      if (auto *p_field{dyn_cast<clang::FieldDecl>(other_fields)}) {
        auto fd = p_field;
        auto port_name{fd->getIdentifier()->getNameStart()};
        LLVM_DEBUG(llvm::dbgs() << " Found sc_out: " << port_name << "\n");
 
        insert_port(out_ports_, fd);
      }
    }
 
    if (sc_inout_field && other_fields) {
      if (auto *p_field{dyn_cast<clang::FieldDecl>(other_fields)}) {
        auto fd = p_field;
        auto port_name{fd->getIdentifier()->getNameStart()};
        LLVM_DEBUG(llvm::dbgs() << " Found sc_inout: " << port_name << "\n");
        insert_port(inout_ports_, fd);
      }
    }
 
    if (sc_signal_field && other_fields) {
      if (auto *p_field{dyn_cast<clang::FieldDecl>(other_fields)}) {
        auto fd = p_field;
        auto signal_name{fd->getIdentifier()->getNameStart()};
        llvm::dbgs() << " Found sc_signal: " << signal_name << "\n";
        insert_port(signal_fields_, fd);
      }
    }
 
    if (sc_stream_in_field && other_fields) {
      if (auto *p_field{dyn_cast<clang::FieldDecl>(other_fields)}) {
        auto fd = p_field;
        auto field_name{fd->getIdentifier()->getNameStart()};
        LLVM_DEBUG(llvm::dbgs()
                   << " Found sc_stream_in: " << field_name << "\n");
        insert_port(instream_ports_, fd);
      }
    }
 
    if (sc_stream_out_field && other_fields) {
      if (auto *p_field{dyn_cast<clang::FieldDecl>(other_fields)}) {
        auto fd = p_field;
        auto field_name{fd->getIdentifier()->getNameStart()};
        LLVM_DEBUG(llvm::dbgs()
                   << " Found sc_stream_out: " << field_name << "\n");
        insert_port(outstream_ports_, fd);
      }
    }
 
    if (sc_rvd_in_field && other_fields) {
      if (auto *p_field{dyn_cast<clang::FieldDecl>(other_fields)}) {
        auto fd = p_field;
        auto field_name{fd->getIdentifier()->getNameStart()};
        LLVM_DEBUG(llvm::dbgs() << " Found sc_rvd_in: " << field_name << "\n");
        insert_port(instream_ports_, fd);
      }
    }
 
    if (sc_rvd_out_field && other_fields) {
      if (auto *p_field{dyn_cast<clang::FieldDecl>(other_fields)}) {
        auto fd = p_field;
        auto field_name{fd->getIdentifier()->getNameStart()};
        LLVM_DEBUG(llvm::dbgs() << " Found sc_rvd_out: " << field_name << "\n");
        insert_port(outstream_ports_, fd);
      }
    }
 
    if (sc_port_field && other_fields) {
      if (auto *p_field{dyn_cast<clang::FieldDecl>(other_fields)}) {
        auto fd = p_field;
        auto field_name{fd->getIdentifier()->getNameStart()};
        LLVM_DEBUG(llvm::dbgs() << " Found sc_port : " << field_name << "\n");
        insert_port(sc_ports_, fd);
      }
    }
 
    auto is_ports{(sc_in_field) || sc_out_field || sc_inout_field ||
                  sc_signal_field || sc_stream_in_field || sc_stream_out_field};
 
    if ((!is_ports)) {
      // These will be either FieldDecl or VarDecl.
      auto fd{other_fvdecl};
      if (fd) {
        LLVM_DEBUG(llvm::dbgs() << "Print out the other fd\n");
 
        if (auto *p_field{dyn_cast<clang::FieldDecl>(fd)}) {
          auto field_name{p_field->getIdentifier()->getNameStart()};
          LLVM_DEBUG(llvm::dbgs()
                     << " Found field other_fields: " << field_name << "\n");
 
        p_field->dump();
          insert_port(other_fields_, p_field);
 
        } else {
          auto *p_var{dyn_cast<clang::VarDecl>(fd)};
          auto field_name{p_var->getIdentifier()->getNameStart()};
          LLVM_DEBUG(llvm::dbgs()
                     << " Found var other_fields: " << field_name << "\n");
          insert_port(other_fields_, p_var);
        }
      }
    }
  }
 
  void dump() {
    printTemplateArguments(clock_ports_);
    printTemplateArguments(in_ports_);
    printTemplateArguments(out_ports_);
    printTemplateArguments(inout_ports_);
    printTemplateArguments(instream_ports_);
    printTemplateArguments(outstream_ports_);
    printTemplateArguments(signal_fields_);
    printTemplateArguments(other_fields_);
    printTemplateArguments(sc_ports_);
    LLVM_DEBUG(llvm::dbgs() << "Identified submodules\n");
    printTemplateArguments(submodules_);
  }
};
};  // namespace sc_ast_matchers
 
#endif